The embodiments described herein relate generally to re-allocation of lanes to a computer bus. More specifically, the embodiments described herein relate to dynamic re-allocation of lanes among adapters received by connectors.
In computer architecture, a bus is a communication system that transfers data between components of a computer system. A local input/output (I/O) bus transfers data between a peripheral component and a computing device. Various types of I/O buses include, but are not limited to, Peripheral Components Interconnect (PCI), Accelerated Graphics Port (AGP), Industry Standard Architecture (ISA), Universal Serial Bus (USB), Micro Channel Architecture (MCA), Enhanced ISA (EISA), Video Electronics Standards Association (VESA), etc.
A PCI Express (PCI-e) bus is an implementation of a PCI computer bus according to a set of PCI Express specifications promulgated by the PCI Special Interest Group. The PCI-e bus uses conventional PCI programming and software concepts, but is based on serial bus architecture as opposed to the parallel bus architecture of the conventional PCI. This physical-layer of the PCI-e computer bus consists of a network of serial interconnections extending from a PCI host bridge or a switch to each peripheral component, referred to herein as an adapter. A connection between the host bridge or the switch to an adapter is referred to as a “link.” The link consists of a collection of one or more lanes used for data communications. Each lane is a set of two unidirectional low voltage differential signaling pairs of transmission pathways such as, for example, traces along a motherboard. Since transmitting data and receiving data are implemented using separate differential pairs, each lane allows for full-duplex serial data communication.
Adapters minimally support single-lane links, and may optionally support wider links composed of two (×2), four (×4), eight (×8), twelve (×12), sixteen (×16), or thirty-two lanes (×32) by providing additional pins on the hardware interface of the adapter that plugs into a PCI-e connector, hereinafter referred to as a connector. The connector may physically support connections for one (×1), two (×2), four (×4), eight (×8), twelve (×12), sixteen (×16), or thirty-two (×32) lanes. Each adapter may be received by any connector that physically supports the same or a greater number of lanes as the lanes physically supported by the adapter. For example an adapter (×8) may be installed into any connector (×8)-(×32). Although the connector and its installed adapter may physically support links with up to thirty-two lanes, an adapter may utilize fewer lanes for data communication than the maximum number of lanes physically supported by the adapter and the connector. For example, for an adapter (×8) installed in a connector (×16), the adapter (×8) may utilize one, two, or four of those eight lanes for data communications. The number of lanes actually utilized for the data communications link between the PCI host bridge or switch and an adapter is typically the highest number of lanes mutually supported by the host bridge, the adapter and its corresponding connector.